Existing networking equipment cards have components that are JTAG (Joint Test Group Action Group) compliant, i.e. meet the requirements of IEEE Standard 1149.1. There are many uses for the chain of components created when JTAG compliant components are assembled together. For example, they can be used for programming devices such as Lattice clock drivers; programming serial EEPROM (Electrically Erasable Programmable Read-Only Memory) and FPGAs (Field Programmable Gate Arrays), both during manufacturing and while in service; CT (Combinational Testing) and interconnect testing during manufacturing; and ILA (Integrated Logic Analyzer) debug access to FPGAs.
One of the challenges in creating a JTAG architecture is that the preferred length of the chain and its starting and stopping point is different depending on the application. A chain which involves all of the JTAG components on a card is required for some manufacturing testing. However, for some applications, only some of the JTAG components may be required. Using a long chain that includes all of the JTAG components may limit the application by the restrictions of the components unnecessary to the application. For example, a component unnecessary to the application may run at slower speed than the necessary components or may be corrupted.
Furthermore, one standard chain structure may not satisfy all needs. In particular, using only one chain may not be the better option for the different functions that can be performed. For example, a shorter chain is more efficient for programming and ILA, while a long chain involving all components is better for testing. Furthermore, different applications may require different chain structures. For example, interconnect testing requires that the chain be controlled with external equipment connected through a header, while in-service upgrades of an EEPROM requires that the chain be controlled locally.